A pipelined memory-efficient architecture for ultra-long variable-size FFT processors

Chen He; Wu Qiang; Gao Zhenbin; Wan Hongxing

doi:10.1109/ICCSIT.2008.160

A pipelined memory-efficient architecture for ultra-long variable-size FFT processors

Chen He^*, Wu Qiang, Gao Zhenbin, Wan Hongxing

^*Corresponding author for this work

School of Optics and Photonics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Citations (Scopus)

Abstract

A scheme of ultra-long variable-size pipelined FFT processor is presented and a prototype is implemented with one FPGA, which may compute various 4 ⁿ (n = 1 ∼ 10) points FFT at a speed as high as 150MHz. The solutions are to transform the one-dimension FFT to two-dimension repeatedly, and propose an efficient twiddle-factor memory compression method. Based on two techniques storage resource of FFT processor can be reduced largely.

Original language	English
Title of host publication	Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008
Pages	357-361
Number of pages	5
DOIs	https://doi.org/10.1109/ICCSIT.2008.160
Publication status	Published - 2008
Event	International Conference on Computer Science and Information Technology, ICCSIT 2008 - Singapore, Singapore Duration: 29 Aug 2008 → 2 Sept 2008

Publication series

Name	Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008

Conference

Conference	International Conference on Computer Science and Information Technology, ICCSIT 2008
Country/Territory	Singapore
City	Singapore
Period	29/08/08 → 2/09/08

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10.1109/ICCSIT.2008.160

Cite this

He, C., Qiang, W., Zhenbin, G., & Hongxing, W. (2008). A pipelined memory-efficient architecture for ultra-long variable-size FFT processors. In Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008 (pp. 357-361). Article 4624891 (Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008). https://doi.org/10.1109/ICCSIT.2008.160

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title = "A pipelined memory-efficient architecture for ultra-long variable-size FFT processors",

abstract = "A scheme of ultra-long variable-size pipelined FFT processor is presented and a prototype is implemented with one FPGA, which may compute various 4 n (n = 1 ∼ 10) points FFT at a speed as high as 150MHz. The solutions are to transform the one-dimension FFT to two-dimension repeatedly, and propose an efficient twiddle-factor memory compression method. Based on two techniques storage resource of FFT processor can be reduced largely.",

author = "Chen He and Wu Qiang and Gao Zhenbin and Wan Hongxing",

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note = "International Conference on Computer Science and Information Technology, ICCSIT 2008 ; Conference date: 29-08-2008 Through 02-09-2008",

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He, C, Qiang, W, Zhenbin, G & Hongxing, W 2008, A pipelined memory-efficient architecture for ultra-long variable-size FFT processors. in Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008., 4624891, Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008, pp. 357-361, International Conference on Computer Science and Information Technology, ICCSIT 2008, Singapore, Singapore, 29/08/08. https://doi.org/10.1109/ICCSIT.2008.160

A pipelined memory-efficient architecture for ultra-long variable-size FFT processors. / He, Chen; Qiang, Wu; Zhenbin, Gao et al.
Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008. 2008. p. 357-361 4624891 (Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A scheme of ultra-long variable-size pipelined FFT processor is presented and a prototype is implemented with one FPGA, which may compute various 4 n (n = 1 ∼ 10) points FFT at a speed as high as 150MHz. The solutions are to transform the one-dimension FFT to two-dimension repeatedly, and propose an efficient twiddle-factor memory compression method. Based on two techniques storage resource of FFT processor can be reduced largely.

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He C, Qiang W, Zhenbin G, Hongxing W. A pipelined memory-efficient architecture for ultra-long variable-size FFT processors. In Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008. 2008. p. 357-361. 4624891. (Proceedings of the International Conference on Computer Science and Information Technology, ICCSIT 2008). doi: 10.1109/ICCSIT.2008.160

A pipelined memory-efficient architecture for ultra-long variable-size FFT processors

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