A parallel CADAMA-based equalization algorithm for FPGA implementation in terahertz communication systems

In terahertz digital wireless communication systems, the performance of the demodulation system in the receiver directly affects the quality of the communication. Channel equalization technology is regarded as an important part of the receiver counteracting damage to terahertz communication system caused by inter-symbol interference (ISI) produced by timing sampling deviation, channel distortions and the nonideal in-band response of ADC and terahertz devices. Compared with non-blind equalization, blind equalization can equalize the channel by using the prior information of the received sequence itself only, and does not require pre-training data. The most commonly used blind equalization algorithm is constant modulus algorithm (CMA), while it does not perform well in non-constant modulus modulation. CMA-Assisted Decision Adjusted Modulus Algorithm (CADAMA) can effectively solve the above problem. Furthermore, traditional serial equalization algorithms are no longer applicable due to the serious imbalance between terahertz band high-speed demodulation requirements and available computing resources. Therefore, this paper develops a high-speed parallel CADAMA equalization scheme for high-order QAM modulation. The general architecture of its implementation which can be widely used in terahertz demodulation systems is presented. Meanwhile, this paper gives the simulation results of the convergence performance of the parallel equalizer, and compares with the serial algorithm to analyze the loss caused by parallelization, which demonstrates the effectiveness and reliability of the parallel equalization algorithm. Finally, the high-speed parallel blind equalization algorithm is implemented in FPGA and applied to the high-speed terahertz band online demodulation system at 15 gigabits per second (Gbps) data rate, 64QAM modulation.