A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP

Wei Zhu; Jian Zhang; Jiawen Wang; Ruitao Wang; Chenguang Li; Kai Wang; Yan Wang

doi:10.1109/VLSITechnologyandCir46769.2022.9830350

A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP

Wei Zhu^*, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kai Wang, Yan Wang

^*Corresponding author for this work

Tsinghua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	128-129
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830350
Publication status	Published - 2022
Externally published	Yes
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830350

Cite this

Zhu, W., Zhang, J., Wang, J., Wang, R., Li, C., Wang, K., & Wang, Y. (2022). A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 128-129). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830350

Zhu, Wei ; Zhang, Jian ; Wang, Jiawen et al. / A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP. 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 128-129 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{905e1fafc6d74882a7636c1ac1b223ab,

title = "A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP",

abstract = "This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.",

author = "Wei Zhu and Jian Zhang and Jiawen Wang and Ruitao Wang and Chenguang Li and Kai Wang and Yan Wang",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830350",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "128--129",

booktitle = "2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022",

address = "United States",

}

Zhu, W, Zhang, J, Wang, J, Wang, R, Li, C, Wang, K & Wang, Y 2022, A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 128-129, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830350

A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP. / Zhu, Wei; Zhang, Jian; Wang, Jiawen et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 128-129 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP

AU - Zhu, Wei

AU - Zhang, Jian

AU - Wang, Jiawen

AU - Wang, Ruitao

AU - Li, Chenguang

AU - Wang, Kai

AU - Wang, Yan

PY - 2022

Y1 - 2022

N2 - This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.

AB - This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.

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DO - 10.1109/VLSITechnologyandCir46769.2022.9830350

M3 - Conference contribution

AN - SCOPUS:85135219428

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 128

EP - 129

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

Y2 - 12 June 2022 through 17 June 2022

ER -

Zhu W, Zhang J, Wang J, Wang R, Li C, Wang K et al. A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 128-129. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830350

A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP

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