A new implementation of dedicated circuit for CORDIC algorithm

The novel technique for efficient implementation of Field programmable gate array (FPGA)-based wave-pipelined Coordinate rotation digital computer (CORDIC) algorithm is presented in this paper. A new clock adjustment scheme which permits finer tuning of the skew between on-chip clocks is developed. All data in FPGA-based Wave pipelined CORDIC circuit (WPCC) pass through the same number of logic gates, and all paths are routed using identical routing resources for achieving best path balancing. Experimental results show that a 256-LUT logic depth WPCC mapped on XC2V6000-4 runs as high as 256 MHz, which is a little slower than the speed of 262 MHz based on the 16-stage Conventional pipelined CORDIC circuit (CPCC) in the same chip. But the latency of the WPCC is 39.1 ns, which is 36% shorter than the latency of 16 clock cycles (i.e. 61.1 ns in this example) of 16-stage CPCC.