TY - JOUR
T1 - A Multi-core Image Acquisition and Storage System with Low-Light Enhancement
AU - Lv, Shidong
AU - Hou, Zhixian
AU - Wang, Chaoyue
AU - Han, Fang
AU - Qi, Quanwen
AU - Liu, Zicheng
AU - Wang, Xinghua
AU - Li, Xiaoran
N1 - Publisher Copyright:
© The Institution of Engineering & Technology 2023.
PY - 2023
Y1 - 2023
N2 - This paper designs and implements an image acquisition and storage system based on the Feiteng processor FT2000/4, which includes five stages: acquisition, processing, compression, storage, and display: Real-time image acquisition through the USB camera, low-light enhancement processing of the captured image, storage of the captured image in the hard disk using JPEG compression coding, reading the image file, decoding and output to the monitor. The system software algorithms use pipelining and Ping-Pong caching methods to significantly optimize system processing speed. As tested, the total time for computing 500 frames of images using a multi-core five-stage pipeline is 8.139658s, with a processing speed of about 61.4fps, which is 3.12 times faster than that of single-core processing. This system achieves efficient operation of image acquisition and storage in the Feiteng processor, optimizes the performance of embedded real-time image acquisition and storage display, and has practical use value.
AB - This paper designs and implements an image acquisition and storage system based on the Feiteng processor FT2000/4, which includes five stages: acquisition, processing, compression, storage, and display: Real-time image acquisition through the USB camera, low-light enhancement processing of the captured image, storage of the captured image in the hard disk using JPEG compression coding, reading the image file, decoding and output to the monitor. The system software algorithms use pipelining and Ping-Pong caching methods to significantly optimize system processing speed. As tested, the total time for computing 500 frames of images using a multi-core five-stage pipeline is 8.139658s, with a processing speed of about 61.4fps, which is 3.12 times faster than that of single-core processing. This system achieves efficient operation of image acquisition and storage in the Feiteng processor, optimizes the performance of embedded real-time image acquisition and storage display, and has practical use value.
KW - Ping-Pong caching
KW - image acquisition
KW - pipelining
UR - http://www.scopus.com/inward/record.url?scp=85203201381&partnerID=8YFLogxK
U2 - 10.1049/icp.2024.1742
DO - 10.1049/icp.2024.1742
M3 - Conference article
AN - SCOPUS:85203201381
SN - 2732-4494
VL - 2023
SP - 3938
EP - 3943
JO - IET Conference Proceedings
JF - IET Conference Proceedings
IS - 47
T2 - IET International Radar Conference 2023, IRC 2023
Y2 - 3 December 2023 through 5 December 2023
ER -