A method of multi-channel pulse acquisition synchronization

Zhanyang Ai; Longhui Wang; Guoman Liu; Chengfa Xu

doi:10.1109/CIRSYSSIM.2017.8023206

A method of multi-channel pulse acquisition synchronization

Zhanyang Ai, Longhui Wang, Guoman Liu, Chengfa Xu

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

In multi-channel pulse acquisition system, it needs to ensure two kinds of synchronization. One is channel synchronization, the other is pulse synchronization. In order to ensure the two synchronizations, a method was proposed by using ADC reset signal to control ADC start-up simultaneously and sequential logic of internal sampling clock fixed. Through the analysis of multi-channel pulse acquisition system architecture, ADC start-up simultaneously could ensure channel synchronization. By the analysis of sequential logic, fixed phase of internal sampling clock could ensure pulse synchronization. Through experiments, channel synchronization deviation is less than 2ps and pulse synchronization deviation is less than 5ps.

Original language	English
Title of host publication	2017 International Conference on Circuits, System and Simulation, ICCSS 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	176-179
Number of pages	4
ISBN (Electronic)	9781538603925
DOIs	https://doi.org/10.1109/CIRSYSSIM.2017.8023206
Publication status	Published - 30 Aug 2017
Event	2017 International Conference on Circuits, System and Simulation, ICCSS 2017 - London, United Kingdom Duration: 14 Jul 2017 → 17 Jul 2017

Publication series

Name	2017 International Conference on Circuits, System and Simulation, ICCSS 2017

Conference

Conference	2017 International Conference on Circuits, System and Simulation, ICCSS 2017
Country/Territory	United Kingdom
City	London
Period	14/07/17 → 17/07/17

Keywords

ADC
Channel synchronization
FPGA
Multi-channel pulse acquisition system
Pulse synchronization

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10.1109/CIRSYSSIM.2017.8023206

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Ai, Z., Wang, L., Liu, G., & Xu, C. (2017). A method of multi-channel pulse acquisition synchronization. In 2017 International Conference on Circuits, System and Simulation, ICCSS 2017 (pp. 176-179). Article 8023206 (2017 International Conference on Circuits, System and Simulation, ICCSS 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CIRSYSSIM.2017.8023206

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title = "A method of multi-channel pulse acquisition synchronization",

abstract = "In multi-channel pulse acquisition system, it needs to ensure two kinds of synchronization. One is channel synchronization, the other is pulse synchronization. In order to ensure the two synchronizations, a method was proposed by using ADC reset signal to control ADC start-up simultaneously and sequential logic of internal sampling clock fixed. Through the analysis of multi-channel pulse acquisition system architecture, ADC start-up simultaneously could ensure channel synchronization. By the analysis of sequential logic, fixed phase of internal sampling clock could ensure pulse synchronization. Through experiments, channel synchronization deviation is less than 2ps and pulse synchronization deviation is less than 5ps.",

keywords = "ADC, Channel synchronization, FPGA, Multi-channel pulse acquisition system, Pulse synchronization",

author = "Zhanyang Ai and Longhui Wang and Guoman Liu and Chengfa Xu",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 International Conference on Circuits, System and Simulation, ICCSS 2017 ; Conference date: 14-07-2017 Through 17-07-2017",

year = "2017",

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doi = "10.1109/CIRSYSSIM.2017.8023206",

language = "English",

series = "2017 International Conference on Circuits, System and Simulation, ICCSS 2017",

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Ai, Z, Wang, L, Liu, G & Xu, C 2017, A method of multi-channel pulse acquisition synchronization. in 2017 International Conference on Circuits, System and Simulation, ICCSS 2017., 8023206, 2017 International Conference on Circuits, System and Simulation, ICCSS 2017, Institute of Electrical and Electronics Engineers Inc., pp. 176-179, 2017 International Conference on Circuits, System and Simulation, ICCSS 2017, London, United Kingdom, 14/07/17. https://doi.org/10.1109/CIRSYSSIM.2017.8023206

A method of multi-channel pulse acquisition synchronization. / Ai, Zhanyang; Wang, Longhui; Liu, Guoman et al.
2017 International Conference on Circuits, System and Simulation, ICCSS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 176-179 8023206 (2017 International Conference on Circuits, System and Simulation, ICCSS 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A method of multi-channel pulse acquisition synchronization

AU - Ai, Zhanyang

AU - Wang, Longhui

AU - Liu, Guoman

AU - Xu, Chengfa

PY - 2017/8/30

Y1 - 2017/8/30

N2 - In multi-channel pulse acquisition system, it needs to ensure two kinds of synchronization. One is channel synchronization, the other is pulse synchronization. In order to ensure the two synchronizations, a method was proposed by using ADC reset signal to control ADC start-up simultaneously and sequential logic of internal sampling clock fixed. Through the analysis of multi-channel pulse acquisition system architecture, ADC start-up simultaneously could ensure channel synchronization. By the analysis of sequential logic, fixed phase of internal sampling clock could ensure pulse synchronization. Through experiments, channel synchronization deviation is less than 2ps and pulse synchronization deviation is less than 5ps.

AB - In multi-channel pulse acquisition system, it needs to ensure two kinds of synchronization. One is channel synchronization, the other is pulse synchronization. In order to ensure the two synchronizations, a method was proposed by using ADC reset signal to control ADC start-up simultaneously and sequential logic of internal sampling clock fixed. Through the analysis of multi-channel pulse acquisition system architecture, ADC start-up simultaneously could ensure channel synchronization. By the analysis of sequential logic, fixed phase of internal sampling clock could ensure pulse synchronization. Through experiments, channel synchronization deviation is less than 2ps and pulse synchronization deviation is less than 5ps.

KW - ADC

KW - Channel synchronization

KW - FPGA

KW - Multi-channel pulse acquisition system

KW - Pulse synchronization

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U2 - 10.1109/CIRSYSSIM.2017.8023206

DO - 10.1109/CIRSYSSIM.2017.8023206

M3 - Conference contribution

AN - SCOPUS:85031663856

T3 - 2017 International Conference on Circuits, System and Simulation, ICCSS 2017

SP - 176

EP - 179

BT - 2017 International Conference on Circuits, System and Simulation, ICCSS 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 International Conference on Circuits, System and Simulation, ICCSS 2017

Y2 - 14 July 2017 through 17 July 2017

ER -

A method of multi-channel pulse acquisition synchronization

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