TY - GEN
T1 - A low-cost spin-on-glass (SOG) liner deposited by vacuum-assisted spin coating technique for via-last ultra-high aspect ratio through-silicon vias
AU - Chen, Xuyan
AU - Ding, Yingtao
AU - Zhang, Ziyue
AU - Xiao, Lei
AU - Wang, Han
AU - Chen, Zhiming
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper presents a spin on glass (SOG) liner formed by vacuum-assisted spin coating (VASC) technique for via last 3D integration applications. In comparison to SiO2 liners produced through traditional methods such as thermal oxidation or chemical vapor deposition (CVD), the proposed approach is simpler and more cost-effective. This methodology successfully achieved a conformal SOG liner within silicon blind vias measuring 6 μm in diameter, 90 μm in depth, and with an aspect ratio of 15:1. The influences of spinning time and SOG solid content on the morphology of the formed liner were investigated in this work. Results show that this method has excellent performance in through silicon vias (TSVs) with small diameter and ultra-high aspect ratio (UHAR). In addition, the deposition of the SOG liner is highly compatible with CMOS technology, and the process can be carried out at a maximum temperature of approximately 200 . As a result, it is suitable for implementation in via-last 3D integration applications.
AB - This paper presents a spin on glass (SOG) liner formed by vacuum-assisted spin coating (VASC) technique for via last 3D integration applications. In comparison to SiO2 liners produced through traditional methods such as thermal oxidation or chemical vapor deposition (CVD), the proposed approach is simpler and more cost-effective. This methodology successfully achieved a conformal SOG liner within silicon blind vias measuring 6 μm in diameter, 90 μm in depth, and with an aspect ratio of 15:1. The influences of spinning time and SOG solid content on the morphology of the formed liner were investigated in this work. Results show that this method has excellent performance in through silicon vias (TSVs) with small diameter and ultra-high aspect ratio (UHAR). In addition, the deposition of the SOG liner is highly compatible with CMOS technology, and the process can be carried out at a maximum temperature of approximately 200 . As a result, it is suitable for implementation in via-last 3D integration applications.
KW - low-cost
KW - spin-on-glass (SOG)
KW - through-silicon vias (TSVs)
KW - ultra-high aspect ratio (UHAR)
KW - vacuum-assisted spin coating (VASC) technique
KW - via-last
UR - http://www.scopus.com/inward/record.url?scp=85191689226&partnerID=8YFLogxK
U2 - 10.1109/ICEPT59018.2023.10492420
DO - 10.1109/ICEPT59018.2023.10492420
M3 - Conference contribution
AN - SCOPUS:85191689226
T3 - 2023 24th International Conference on Electronic Packaging Technology, ICEPT 2023
BT - 2023 24th International Conference on Electronic Packaging Technology, ICEPT 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th International Conference on Electronic Packaging Technology, ICEPT 2023
Y2 - 8 August 2023 through 11 August 2023
ER -