A high-precision hardware-efficient radix-2^k FFT processor for SAR imaging system

This paper presents a high-precision, hardware-efficient FFT processor for an on-board SAR (synthetic aperture radar) imaging system. To meet the high resolution imaging and big data granularity processing requirements, a radix-2^k mixed FFT algorithm is proposed. The mixed radix FFT algorithm reduces the number of complex multiplication and the size of twiddle factor memory. To further reduce hardware resource and improve FFT precision, sufficient fixed-point simulation is performed for the fixedpoint FFT processor design. As a proof of concept, a 32768-point fixed-point processor is implemented on XC6VCX240T FPGA platform. The proposed pipelined FFT processor achieves a signal-to-quantization noise ratio (SQNR) of 47.3 dB at 18-bit internal wordlength. Compared with Xilinx FFT v7.1 IP core, the results demonstrate that our design saves at least 11% memory and 57% arithmetic elements.