A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS

Haikun Jia; Baoyong Chi; Lixue Kuang; Wei Zhu; Zhiping Wang; Feng Ma; Zhihua Wang

doi:10.1109/ASSCC.2015.7387438

A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS

Haikun Jia, Baoyong Chi, Lixue Kuang, Wei Zhu, Zhiping Wang, Feng Ma, Zhihua Wang

Tsinghua University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

This paper presented a frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS process. The FMCW signal is generated by a fractional-N PLL. The frequency doubling scheme can lower down the frequency of the PLL, reduce the required phase shifting range of phase shifter and the design complexity of the LO distributed network. The FMCW chirp bandwidth is 1.93 GHz from 76.92 to 78.85 GHz, while the root-mean-square frequency error is 674 kHz. The transmitting power is 12.9∼13.2 dBm. The receive conversion gain is programmable from 47.8 dB to 100.7 dB. The two-path receiver noise figure is 10 dB and 6.6 dB at 400 kHz and 3.3 MHz IF frequencies, respectively. The transceiver consumes 343 mW power.

Original language	English
Title of host publication	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467371919
DOIs	https://doi.org/10.1109/ASSCC.2015.7387438
Publication status	Published - 19 Jan 2016
Externally published	Yes
Event	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China Duration: 9 Nov 2015 → 11 Nov 2015

Publication series

Name	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Conference

Conference	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
Country/Territory	China
City	Xiamen, Fujian
Period	9/11/15 → 11/11/15

Keywords

CMOS
FMCW
frequency doubling
phased array

Access to Document

10.1109/ASSCC.2015.7387438

Cite this

Jia, H., Chi, B., Kuang, L., Zhu, W., Wang, Z., Ma, F., & Wang, Z. (2016). A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings Article 7387438 (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2015.7387438

@inproceedings{08f027f8bd3f41a490252bd20f3fc1b4,

title = "A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS",

abstract = "This paper presented a frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS process. The FMCW signal is generated by a fractional-N PLL. The frequency doubling scheme can lower down the frequency of the PLL, reduce the required phase shifting range of phase shifter and the design complexity of the LO distributed network. The FMCW chirp bandwidth is 1.93 GHz from 76.92 to 78.85 GHz, while the root-mean-square frequency error is 674 kHz. The transmitting power is 12.9∼13.2 dBm. The receive conversion gain is programmable from 47.8 dB to 100.7 dB. The two-path receiver noise figure is 10 dB and 6.6 dB at 400 kHz and 3.3 MHz IF frequencies, respectively. The transceiver consumes 343 mW power.",

keywords = "CMOS, FMCW, frequency doubling, phased array",

author = "Haikun Jia and Baoyong Chi and Lixue Kuang and Wei Zhu and Zhiping Wang and Feng Ma and Zhihua Wang",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 ; Conference date: 09-11-2015 Through 11-11-2015",

year = "2016",

month = jan,

day = "19",

doi = "10.1109/ASSCC.2015.7387438",

language = "English",

series = "2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings",

address = "United States",

}

Jia, H, Chi, B, Kuang, L, Zhu, W, Wang, Z, Ma, F & Wang, Z 2016, A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS. in 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings., 7387438, 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xiamen, Fujian, China, 9/11/15. https://doi.org/10.1109/ASSCC.2015.7387438

A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS. / Jia, Haikun; Chi, Baoyong; Kuang, Lixue et al.
2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. 7387438 (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS

AU - Jia, Haikun

AU - Chi, Baoyong

AU - Kuang, Lixue

AU - Zhu, Wei

AU - Wang, Zhiping

AU - Ma, Feng

AU - Wang, Zhihua

PY - 2016/1/19

Y1 - 2016/1/19

N2 - This paper presented a frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS process. The FMCW signal is generated by a fractional-N PLL. The frequency doubling scheme can lower down the frequency of the PLL, reduce the required phase shifting range of phase shifter and the design complexity of the LO distributed network. The FMCW chirp bandwidth is 1.93 GHz from 76.92 to 78.85 GHz, while the root-mean-square frequency error is 674 kHz. The transmitting power is 12.9∼13.2 dBm. The receive conversion gain is programmable from 47.8 dB to 100.7 dB. The two-path receiver noise figure is 10 dB and 6.6 dB at 400 kHz and 3.3 MHz IF frequencies, respectively. The transceiver consumes 343 mW power.

AB - This paper presented a frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS process. The FMCW signal is generated by a fractional-N PLL. The frequency doubling scheme can lower down the frequency of the PLL, reduce the required phase shifting range of phase shifter and the design complexity of the LO distributed network. The FMCW chirp bandwidth is 1.93 GHz from 76.92 to 78.85 GHz, while the root-mean-square frequency error is 674 kHz. The transmitting power is 12.9∼13.2 dBm. The receive conversion gain is programmable from 47.8 dB to 100.7 dB. The two-path receiver noise figure is 10 dB and 6.6 dB at 400 kHz and 3.3 MHz IF frequencies, respectively. The transceiver consumes 343 mW power.

KW - CMOS

KW - FMCW

KW - frequency doubling

KW - phased array

UR - http://www.scopus.com/inward/record.url?scp=84963806001&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2015.7387438

DO - 10.1109/ASSCC.2015.7387438

M3 - Conference contribution

AN - SCOPUS:84963806001

T3 - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

BT - 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015

Y2 - 9 November 2015 through 11 November 2015

ER -

Jia H, Chi B, Kuang L, Zhu W, Wang Z, Ma F et al. A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. 7387438. (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). doi: 10.1109/ASSCC.2015.7387438

A frequency doubling two-path phased-array FMCW radar transceiver in 65nm CMOS

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this