A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation

Hao Zhang; Xinghua Wang; Lei Zhang; Zhijing Zhang

doi:10.1109/IEEE-IWS.2018.8400824

A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation

Hao Zhang, Xinghua Wang, Lei Zhang, Zhijing Zhang

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

This paper proposes a single-channel 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 90nm CMOS process with a 1.2-V supply voltage. By using a partial-monotonic switching sequences, the common-mode voltage variation is reduced efficiently. The binary redundancy compensation technique is adopted to solve comparator errors caused by dynamic offset and DAC settling. Compared to the conventional structure, the proposed method reduces the total capacitance by 4x, which enhances the speed and decreases the chip area. The simulation results indicate that the prototype achieves a SNDR of 60.27dB and an ENOB of 9.72b with a 58.134MHz input signal at 120MHz sampling rate, while only consuming 3.24mW power.

Original language	English
Title of host publication	2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781538663462
DOIs	https://doi.org/10.1109/IEEE-IWS.2018.8400824
Publication status	Published - 29 Jun 2018
Event	2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Chengdu, China Duration: 6 May 2018 → 9 May 2018

Publication series

Name	2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings

Conference

Conference	2018 IEEE MTT-S International Wireless Symposium, IWS 2018
Country/Territory	China
City	Chengdu
Period	6/05/18 → 9/05/18

Keywords

Analog-to-digital converter(ADC)
redundancy compensation
successive approximation register(SAR)

Access to Document

10.1109/IEEE-IWS.2018.8400824

Cite this

Zhang, H., Wang, X., Zhang, L., & Zhang, Z. (2018). A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation. In 2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings (pp. 1-3). (2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEEE-IWS.2018.8400824

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title = "A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation",

abstract = "This paper proposes a single-channel 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 90nm CMOS process with a 1.2-V supply voltage. By using a partial-monotonic switching sequences, the common-mode voltage variation is reduced efficiently. The binary redundancy compensation technique is adopted to solve comparator errors caused by dynamic offset and DAC settling. Compared to the conventional structure, the proposed method reduces the total capacitance by 4x, which enhances the speed and decreases the chip area. The simulation results indicate that the prototype achieves a SNDR of 60.27dB and an ENOB of 9.72b with a 58.134MHz input signal at 120MHz sampling rate, while only consuming 3.24mW power.",

keywords = "Analog-to-digital converter(ADC), redundancy compensation, successive approximation register(SAR)",

author = "Hao Zhang and Xinghua Wang and Lei Zhang and Zhijing Zhang",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE MTT-S International Wireless Symposium, IWS 2018 ; Conference date: 06-05-2018 Through 09-05-2018",

year = "2018",

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language = "English",

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Zhang, H, Wang, X, Zhang, L & Zhang, Z 2018, A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation. in 2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings. 2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2018 IEEE MTT-S International Wireless Symposium, IWS 2018, Chengdu, China, 6/05/18. https://doi.org/10.1109/IEEE-IWS.2018.8400824

A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation. / Zhang, Hao; Wang, Xinghua; Zhang, Lei et al.
2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-3 (2018 IEEE MTT-S International Wireless Symposium, IWS 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Zhang, Hao

AU - Wang, Xinghua

AU - Zhang, Lei

AU - Zhang, Zhijing

PY - 2018/6/29

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N2 - This paper proposes a single-channel 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 90nm CMOS process with a 1.2-V supply voltage. By using a partial-monotonic switching sequences, the common-mode voltage variation is reduced efficiently. The binary redundancy compensation technique is adopted to solve comparator errors caused by dynamic offset and DAC settling. Compared to the conventional structure, the proposed method reduces the total capacitance by 4x, which enhances the speed and decreases the chip area. The simulation results indicate that the prototype achieves a SNDR of 60.27dB and an ENOB of 9.72b with a 58.134MHz input signal at 120MHz sampling rate, while only consuming 3.24mW power.

AB - This paper proposes a single-channel 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 90nm CMOS process with a 1.2-V supply voltage. By using a partial-monotonic switching sequences, the common-mode voltage variation is reduced efficiently. The binary redundancy compensation technique is adopted to solve comparator errors caused by dynamic offset and DAC settling. Compared to the conventional structure, the proposed method reduces the total capacitance by 4x, which enhances the speed and decreases the chip area. The simulation results indicate that the prototype achieves a SNDR of 60.27dB and an ENOB of 9.72b with a 58.134MHz input signal at 120MHz sampling rate, while only consuming 3.24mW power.

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A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation

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