10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS

Lei Tian; Zhigong Wang; Haitao Chen; Tingting Xie; Jianhua Lu; Rui Tao; Yi Dong; Shizhong Xie

doi:10.1117/12.444544

10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS

Lei Tian, Zhigong Wang, Haitao Chen, Tingting Xie, Jianhua Lu, Rui Tao, Yi Dong, Shizhong Xie

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This paper describes a 1:4 demultiplexer in a standard 0.25 μm CMOS. A tree-type structure is used to reduce the clock frequency and the SCL (Source Couple Logic) is used to construct high speed DFF. The chip occupies 1 mm² area. It consumes 693 mW from a 3.3 V supply. The operating bit rates is higher than 10 Gb/s.

Original language	English
Pages (from-to)	121-124
Number of pages	4
Journal	Proceedings of SPIE - The International Society for Optical Engineering
Volume	4603
DOIs	https://doi.org/10.1117/12.444544
Publication status	Published - 2001
Externally published	Yes

Keywords

0.25 μm CMOS
1:4 Demultiplexer
High-speed ICs
SCL
SDH system

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10.1117/12.444544

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Tian, L., Wang, Z., Chen, H., Xie, T., Lu, J., Tao, R., Dong, Y., & Xie, S. (2001). 10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS. Proceedings of SPIE - The International Society for Optical Engineering, 4603, 121-124. https://doi.org/10.1117/12.444544

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AU - Chen, Haitao

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AU - Tao, Rui

AU - Dong, Yi

AU - Xie, Shizhong

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10-Gb/s 1:4 demultiplexer in 0.25 μm CMOS

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Keywords

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