蒙哥马利模乘算法改进及硬件实现

In cryptographic application scenarios such as embedded and IoT, it is necessary to balance the performance and resource consumption of cryptographic implementation to find the best balance of comprehensive efficiency. As the core computing module of public key cryptographic algorithms such as Rivest-Shamir-Adleman algorithm (RSA) and elliptic curve cryptography (ECC), the resource consumption and computing speed of the modulo multiplier directly determine the overall performance of the upper layer cryptographic algorithms. The proposed efficient low-latency Montgomery modulo multiplication was designed to effectively reduce the amount of operations and the complexity of hardware design. On this basis, the length of the critical path in the modulo multiplier was arranged to be further reduced by using the proposed 5-2 low-latency adder in combination to improve the algorithm operation efficiency. The system main frequency of the 1024-bit modulo module implemented on the Xilinx-K7 series platform can reach 278 MHz, while the area-time-product （ATP） is improved by more than 15% compared with the existing similar algorithms, and the overall efficiency is optimal. The results show that the improved Montgomery modulo multiplication algorithm can give a low hardware resource consumption, being suitable for lightweight cryptosystems such as IoT.