Design of a low-power 1.5 Gb/s CMOS 1:4 demultiplexer IC

Wencai Lu; Zhigong Wang; Lei Tian; Tingting Xie; Yi Dong; Shizhong Xie

doi:10.1117/12.444554

Design of a low-power 1.5 Gb/s CMOS 1:4 demultiplexer IC

Wencai Lu, Zhigong Wang, Lei Tian, Tingting Xie, Yi Dong, Shizhong Xie

科研成果: 期刊稿件 › 文章 › 同行评审

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摘要

This paper presents a 1.5 Gb/s 1:4 demultiplexer IC. It is implemented in a tree-type architecture. The basic cell, i.e. the Flip-Flops, is built up in CMOS pseudo-static logic. The IC was realized in a 0.25 μm CMOS technology, and has been measured in an ultra-high speed setup. Opening eye diagrams have been obtained at bit rates up to 1.5 Gb/s. The phase margin at 1.5 Gb/s is greater than 180 degree. The power dissipation of the function core circuit is only 9.5 mW under a supply voltage of 2.5 V.

源语言	英语
页（从-至）	174-177
页数	4
期刊	Proceedings of SPIE - The International Society for Optical Engineering
卷	4603
DOI	https://doi.org/10.1117/12.444554
出版状态	已出版 - 2001
已对外发布	是

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abstract = "This paper presents a 1.5 Gb/s 1:4 demultiplexer IC. It is implemented in a tree-type architecture. The basic cell, i.e. the Flip-Flops, is built up in CMOS pseudo-static logic. The IC was realized in a 0.25 μm CMOS technology, and has been measured in an ultra-high speed setup. Opening eye diagrams have been obtained at bit rates up to 1.5 Gb/s. The phase margin at 1.5 Gb/s is greater than 180 degree. The power dissipation of the function core circuit is only 9.5 mW under a supply voltage of 2.5 V.",

keywords = "CMOS, Demultiplexer (DEMUX), High speed IC, Low power IC, Synchronous digital hierarchy (SDH)",

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T1 - Design of a low-power 1.5 Gb/s CMOS 1:4 demultiplexer IC

AU - Lu, Wencai

AU - Wang, Zhigong

AU - Tian, Lei

AU - Xie, Tingting

AU - Dong, Yi

AU - Xie, Shizhong

PY - 2001

Y1 - 2001

N2 - This paper presents a 1.5 Gb/s 1:4 demultiplexer IC. It is implemented in a tree-type architecture. The basic cell, i.e. the Flip-Flops, is built up in CMOS pseudo-static logic. The IC was realized in a 0.25 μm CMOS technology, and has been measured in an ultra-high speed setup. Opening eye diagrams have been obtained at bit rates up to 1.5 Gb/s. The phase margin at 1.5 Gb/s is greater than 180 degree. The power dissipation of the function core circuit is only 9.5 mW under a supply voltage of 2.5 V.

AB - This paper presents a 1.5 Gb/s 1:4 demultiplexer IC. It is implemented in a tree-type architecture. The basic cell, i.e. the Flip-Flops, is built up in CMOS pseudo-static logic. The IC was realized in a 0.25 μm CMOS technology, and has been measured in an ultra-high speed setup. Opening eye diagrams have been obtained at bit rates up to 1.5 Gb/s. The phase margin at 1.5 Gb/s is greater than 180 degree. The power dissipation of the function core circuit is only 9.5 mW under a supply voltage of 2.5 V.

KW - CMOS

KW - Demultiplexer (DEMUX)

KW - High speed IC

KW - Low power IC

KW - Synchronous digital hierarchy (SDH)

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Design of a low-power 1.5 Gb/s CMOS 1:4 demultiplexer IC

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