Abstract
This paper provides a new approach for the formation of polymer liner for low-$k$ high-aspect-ratio through-silicon-vias involved in via-last backside-via 3-D integration applications. The approach mentioned, referred to as vacuum-assisted spin coating technique in this paper, is formed by combining a conventional spin coating technique and a vacuum treatment. Silicon blind vias with a diameter of 6~ μ m} and an aspect ratio of ∼ 8 were conformably coated on their sidewall with polyimide liner with the minimum step coverage ∼ 30 % by this approach. Impacts of via geometric parameters and wafer sizes on step coverage were investigated. Electrical characteristics were evaluated with a trench capacitor structure of which the insulator layer was formed by the vacuum-assisted spin coating technique. The minimum capacitance density of 5.3 nF/cm2 and the leakage current density of ∼ 3 nA/cm2 at a biased voltage of 5 V were obtained. The proposed vacuum-assisted spin coating technique is a simple, feasible, and cost-effective approach for 3-D integration applications.
Original language | English |
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Article number | 7397981 |
Pages (from-to) | 501-509 |
Number of pages | 9 |
Journal | IEEE Transactions on Components, Packaging and Manufacturing Technology |
Volume | 6 |
Issue number | 4 |
DOIs | |
Publication status | Published - Apr 2016 |
Keywords
- 3-D integration
- backside-via integration
- polymer liner
- through-silicon-vias (TSVs)
- vacuum-assisted spin coating
- via-last.