Pipelined implementation of serial comparison based iterative sort on FPGA

Sorting is a classic problem in computer science. Different kinds of sorting algorithms are required in different application scenarios. With regard to the real-time data processing applications implemented on FPGA, a faster throughput and more resource efficient sorting algorithm is needed to complete the data sorting. And the pipelined implementation of sorting algorithm is essential for improving the overall throughput. In this paper, a serial comparison based iterative sort algorithm is proposed and its implementation on FPGA is elaborated. To take advantages of the parallel characteristics of FPGA, the pipelined sorting module is realized by concatenating multiple serial comparison sorting submodules. Compared to other sorting algorithms implemented on FPGA, the serial comparison based iterative sort algorithm has the merit of requiring fewer resource consumptions, consuming less executing time and generating faster overall data throughput. The algorithm and its pipelined implementation have been successfully applied to the median filter of OS-CFAR processing in millimetre-wave MIMO radar, and their performance have been validated.