Large dynamic range accurate digitally programmable delay line with 250-ps resolution

Jiaqi Li; Zhe Zheng; Min Liu; Siliang Wu

doi:10.1109/ICOSP.2006.345484

Large dynamic range accurate digitally programmable delay line with 250-ps resolution

Jiaqi Li^*, Zhe Zheng, Min Liu, Siliang Wu

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Citations (Scopus)

Abstract

This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts Time-to-Digital conversion(TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of ±1ppm, and when the delay range is within 0-0.1 ms, the delay accuracy of our design can reach ±350 ps.

Original language	English
Title of host publication	8th International Conference on Signal Processing, ICSP 2006
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	0780397371, 9780780397378
DOIs	https://doi.org/10.1109/ICOSP.2006.345484
Publication status	Published - 2006
Event	8th International Conference on Signal Processing, ICSP 2006 - Guilin, China Duration: 16 Nov 2006 → 20 Nov 2006

Publication series

Name	International Conference on Signal Processing Proceedings, ICSP
Volume	1

Conference

Conference	8th International Conference on Signal Processing, ICSP 2006
Country/Territory	China
City	Guilin
Period	16/11/06 → 20/11/06

Access to Document

10.1109/ICOSP.2006.345484

Cite this

Li, J., Zheng, Z., Liu, M., & Wu, S. (2006). Large dynamic range accurate digitally programmable delay line with 250-ps resolution. In 8th International Conference on Signal Processing, ICSP 2006 Article 4128909 (International Conference on Signal Processing Proceedings, ICSP; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICOSP.2006.345484

@inproceedings{5e00e519976445d2a37844d07ba761b1,

title = "Large dynamic range accurate digitally programmable delay line with 250-ps resolution",

abstract = "This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts Time-to-Digital conversion(TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of ±1ppm, and when the delay range is within 0-0.1 ms, the delay accuracy of our design can reach ±350 ps.",

author = "Jiaqi Li and Zhe Zheng and Min Liu and Siliang Wu",

year = "2006",

doi = "10.1109/ICOSP.2006.345484",

language = "English",

isbn = "0780397371",

series = "International Conference on Signal Processing Proceedings, ICSP",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "8th International Conference on Signal Processing, ICSP 2006",

address = "United States",

note = "8th International Conference on Signal Processing, ICSP 2006 ; Conference date: 16-11-2006 Through 20-11-2006",

}

Li, J, Zheng, Z, Liu, M & Wu, S 2006, Large dynamic range accurate digitally programmable delay line with 250-ps resolution. in 8th International Conference on Signal Processing, ICSP 2006., 4128909, International Conference on Signal Processing Proceedings, ICSP, vol. 1, Institute of Electrical and Electronics Engineers Inc., 8th International Conference on Signal Processing, ICSP 2006, Guilin, China, 16/11/06. https://doi.org/10.1109/ICOSP.2006.345484

Large dynamic range accurate digitally programmable delay line with 250-ps resolution. / Li, Jiaqi; Zheng, Zhe; Liu, Min et al.
8th International Conference on Signal Processing, ICSP 2006. Institute of Electrical and Electronics Engineers Inc., 2006. 4128909 (International Conference on Signal Processing Proceedings, ICSP; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Large dynamic range accurate digitally programmable delay line with 250-ps resolution

AU - Li, Jiaqi

AU - Zheng, Zhe

AU - Liu, Min

AU - Wu, Siliang

PY - 2006

Y1 - 2006

N2 - This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts Time-to-Digital conversion(TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of ±1ppm, and when the delay range is within 0-0.1 ms, the delay accuracy of our design can reach ±350 ps.

AB - This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts Time-to-Digital conversion(TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of ±1ppm, and when the delay range is within 0-0.1 ms, the delay accuracy of our design can reach ±350 ps.

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DO - 10.1109/ICOSP.2006.345484

M3 - Conference contribution

AN - SCOPUS:34249288335

SN - 0780397371

SN - 9780780397378

T3 - International Conference on Signal Processing Proceedings, ICSP

BT - 8th International Conference on Signal Processing, ICSP 2006

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 8th International Conference on Signal Processing, ICSP 2006

Y2 - 16 November 2006 through 20 November 2006

ER -

Large dynamic range accurate digitally programmable delay line with 250-ps resolution

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