Large dynamic range accurate digitally programmable delay line with 250-ps resolution

Jiaqi Li*, Zhe Zheng, Min Liu, Siliang Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

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Abstract

This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts Time-to-Digital conversion(TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of ±1ppm, and when the delay range is within 0-0.1 ms, the delay accuracy of our design can reach ±350 ps.

Original languageEnglish
Title of host publication8th International Conference on Signal Processing, ICSP 2006
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)0780397371, 9780780397378
DOIs
Publication statusPublished - 2006
Event8th International Conference on Signal Processing, ICSP 2006 - Guilin, China
Duration: 16 Nov 200620 Nov 2006

Publication series

NameInternational Conference on Signal Processing Proceedings, ICSP
Volume1

Conference

Conference8th International Conference on Signal Processing, ICSP 2006
Country/TerritoryChina
CityGuilin
Period16/11/0620/11/06

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Li, J., Zheng, Z., Liu, M., & Wu, S. (2006). Large dynamic range accurate digitally programmable delay line with 250-ps resolution. In 8th International Conference on Signal Processing, ICSP 2006 Article 4128909 (International Conference on Signal Processing Proceedings, ICSP; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICOSP.2006.345484