@inproceedings{5e00e519976445d2a37844d07ba761b1,
title = "Large dynamic range accurate digitally programmable delay line with 250-ps resolution",
abstract = "This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts Time-to-Digital conversion(TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of ±1ppm, and when the delay range is within 0-0.1 ms, the delay accuracy of our design can reach ±350 ps.",
author = "Jiaqi Li and Zhe Zheng and Min Liu and Siliang Wu",
year = "2006",
doi = "10.1109/ICOSP.2006.345484",
language = "English",
isbn = "0780397371",
series = "International Conference on Signal Processing Proceedings, ICSP",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "8th International Conference on Signal Processing, ICSP 2006",
address = "United States",
note = "8th International Conference on Signal Processing, ICSP 2006 ; Conference date: 16-11-2006 Through 20-11-2006",
}