Graphene/Si CMOS Hybrid hall integrated circuits

Le Huang, Huilong Xu, Zhiyong Zhang, Chengying Chen, Jianhua Jiang, Xiaomeng Ma, Bingyan Chen, Zishen Li, Hua Zhong, Lian Mao Peng*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

56 Citations (Scopus)

Abstract

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18â um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Original languageEnglish
Article number5548
JournalScientific Reports
Volume4
DOIs
Publication statusPublished - 7 Jul 2014
Externally publishedYes

Fingerprint

Dive into the research topics of 'Graphene/Si CMOS Hybrid hall integrated circuits'. Together they form a unique fingerprint.

Cite this