FPGA-based efficient programmable polyphase FIR filter

He Chen; Cheng Huan Xiong; Shun An Zhong; Hua Wang

FPGA-based efficient programmable polyphase FIR filter

He Chen^*, Cheng Huan Xiong, Shun An Zhong, Hua Wang

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx Virtex II-v1500 device and operates at the maximum sampling frequency of 160 MHz.

Original language	English
Pages (from-to)	4-8
Number of pages	5
Journal	Journal of Beijing Institute of Technology (English Edition)
Volume	14
Issue number	1
Publication status	Published - Mar 2005

Keywords

Field programmable gate array (FPGA)
Finite impulse response (FIR) filter
Polyphase

Cite this

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title = "FPGA-based efficient programmable polyphase FIR filter",

abstract = "The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx Virtex II-v1500 device and operates at the maximum sampling frequency of 160 MHz.",

keywords = "Field programmable gate array (FPGA), Finite impulse response (FIR) filter, Polyphase",

author = "He Chen and Xiong, {Cheng Huan} and Zhong, {Shun An} and Hua Wang",

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AU - Chen, He

AU - Xiong, Cheng Huan

AU - Zhong, Shun An

AU - Wang, Hua

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N2 - The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx Virtex II-v1500 device and operates at the maximum sampling frequency of 160 MHz.

AB - The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx Virtex II-v1500 device and operates at the maximum sampling frequency of 160 MHz.

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KW - Finite impulse response (FIR) filter

KW - Polyphase

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FPGA-based efficient programmable polyphase FIR filter

Abstract

Keywords

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