Design of low-power quaternary flip-flop based on dynamic source-coupled logic

Haixia Wu; Shunan Zhong; Zhentao Sun; Xiaonan Qu; Yueyang Chen

doi:10.1109/ICECC.2011.6066389

Design of low-power quaternary flip-flop based on dynamic source-coupled logic

Haixia Wu^*, Shunan Zhong, Zhentao Sun, Xiaonan Qu, Yueyang Chen

^*Corresponding author for this work

School of Integrated Circuits and Electronics

Beijing Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Citations (Scopus)

Abstract

A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18m CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.

Original language	English
Title of host publication	2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings
Pages	826-828
Number of pages	3
DOIs	https://doi.org/10.1109/ICECC.2011.6066389
Publication status	Published - 2011
Event	2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Ningbo, China Duration: 9 Sept 2011 → 11 Sept 2011

Publication series

Name	2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings

Conference

Conference	2011 International Conference on Electronics, Communications and Control, ICECC 2011
Country/Territory	China
City	Ningbo
Period	9/09/11 → 11/09/11

Keywords

Multiple-value Logic
Quaternary Flip-Flop
Source-coupled Logic

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10.1109/ICECC.2011.6066389

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Wu, H., Zhong, S., Sun, Z., Qu, X., & Chen, Y. (2011). Design of low-power quaternary flip-flop based on dynamic source-coupled logic. In 2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings (pp. 826-828). Article 6066389 (2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings). https://doi.org/10.1109/ICECC.2011.6066389

@inproceedings{c33fd99739a14659b55aed9fb7b15aaf,

title = "Design of low-power quaternary flip-flop based on dynamic source-coupled logic",

abstract = "A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18m CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.",

keywords = "Multiple-value Logic, Quaternary Flip-Flop, Source-coupled Logic",

author = "Haixia Wu and Shunan Zhong and Zhentao Sun and Xiaonan Qu and Yueyang Chen",

year = "2011",

doi = "10.1109/ICECC.2011.6066389",

language = "English",

isbn = "9781457703218",

series = "2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings",

pages = "826--828",

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note = "2011 International Conference on Electronics, Communications and Control, ICECC 2011 ; Conference date: 09-09-2011 Through 11-09-2011",

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Wu, H, Zhong, S, Sun, Z, Qu, X & Chen, Y 2011, Design of low-power quaternary flip-flop based on dynamic source-coupled logic. in 2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings., 6066389, 2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings, pp. 826-828, 2011 International Conference on Electronics, Communications and Control, ICECC 2011, Ningbo, China, 9/09/11. https://doi.org/10.1109/ICECC.2011.6066389

Design of low-power quaternary flip-flop based on dynamic source-coupled logic. / Wu, Haixia; Zhong, Shunan; Sun, Zhentao et al.
2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings. 2011. p. 826-828 6066389 (2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Wu, Haixia

AU - Zhong, Shunan

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AU - Qu, Xiaonan

AU - Chen, Yueyang

PY - 2011

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N2 - A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18m CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.

AB - A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18m CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.

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KW - Quaternary Flip-Flop

KW - Source-coupled Logic

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SN - 9781457703218

T3 - 2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings

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Wu H, Zhong S, Sun Z, Qu X, Chen Y. Design of low-power quaternary flip-flop based on dynamic source-coupled logic. In 2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings. 2011. p. 826-828. 6066389. (2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings). doi: 10.1109/ICECC.2011.6066389

Design of low-power quaternary flip-flop based on dynamic source-coupled logic

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