Design of low-power quaternary flip-flop based on dynamic source-coupled logic

Haixia Wu*, Shunan Zhong, Zhentao Sun, Xiaonan Qu, Yueyang Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Citations (Scopus)

Abstract

A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18m CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.

Original languageEnglish
Title of host publication2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings
Pages826-828
Number of pages3
DOIs
Publication statusPublished - 2011
Event2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Ningbo, China
Duration: 9 Sept 201111 Sept 2011

Publication series

Name2011 International Conference on Electronics, Communications and Control, ICECC 2011 - Proceedings

Conference

Conference2011 International Conference on Electronics, Communications and Control, ICECC 2011
Country/TerritoryChina
CityNingbo
Period9/09/1111/09/11

Keywords

  • Multiple-value Logic
  • Quaternary Flip-Flop
  • Source-coupled Logic

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