Design of a large point FFT processor with configurable transform length

Yu Xie; Yang Kai Feng; Chen Yang; Yi Zhuang Xie; He Chen

Design of a large point FFT processor with configurable transform length

Yu Xie, Yang Kai Feng, Chen Yang, Yi Zhuang Xie^*, He Chen

^*Corresponding author for this work

School of Information and Electronics

Beijing Institute of Technology

Research output: Contribution to conference › Paper › peer-review

3 Citations (Scopus)

Abstract

In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.

Original language	English
Publication status	Published - 2015
Event	IET International Radar Conference 2015 - Hangzhou, China Duration: 14 Oct 2015 → 16 Oct 2015

Conference

Conference	IET International Radar Conference 2015
Country/Territory	China
City	Hangzhou
Period	14/10/15 → 16/10/15

Keywords

Configurable
FFT
FPGA
Large point
Real-time

Cite this

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title = "Design of a large point FFT processor with configurable transform length",

abstract = "In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.",

keywords = "Configurable, FFT, FPGA, Large point, Real-time",

author = "Yu Xie and Feng, {Yang Kai} and Chen Yang and Xie, {Yi Zhuang} and He Chen",

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note = "IET International Radar Conference 2015 ; Conference date: 14-10-2015 Through 16-10-2015",

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AU - Xie, Yu

AU - Feng, Yang Kai

AU - Yang, Chen

AU - Xie, Yi Zhuang

AU - Chen, He

PY - 2015

Y1 - 2015

N2 - In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.

AB - In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16∼128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.

KW - Configurable

KW - FFT

KW - FPGA

KW - Large point

KW - Real-time

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M3 - Paper

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T2 - IET International Radar Conference 2015

Y2 - 14 October 2015 through 16 October 2015

ER -

Design of a large point FFT processor with configurable transform length

Abstract

Conference

Keywords

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