Algorithm and realization of high dynamic satellite signal doppler simulation based on FPGA

Under the circumstances of satellite out of orbit or experiment test in laboratory, in order to validate performance of satellite positioning system, satellite signal simulator is needed to simulate real satellite signal at various conditions. Relative high speed movement between satellite and receiver makes the carrier and code frequency of received signal changed in dynamic environment. Doppler frequency shift simulation is a key technique that must be solved for the high dynamic satellite signal simulator. The satellite signal simulation architecture (e.g. computer + DSP + FPGA + DAC + RF module) based on Software Define Radio is widely used nowadays. Digital intermediate frequency satellite modulation signal is generated by FPGA. The precision of approximation to Doppler frequency implemented on FPGA determines performance of high dynamic simulator. This paper proposes a three-stage cascaded DDS Doppler implementation architecture according to real high dynamic model with acceleration and jerk. The new architecture overcomes the disadvantages of traditional DDS, and can be used in the accurate simulation of Doppler frequency. In section 2, the problem definition of simulated GNSS signal under high dynamic condition is given and traditional DDS architecture is described. Section 3 presents the third-order DDS model and gives the derivation of its output phase expression step by step. The corresponding relationships between the design parameters of DDS and signal Doppler are analyzed and a guide line to choose proper parameters is provided. Simulation instances in high dynamic motion with acceleration and jerk are discussed in section 4. The performance of third-order DDS is verified by software simulation and hardware test. Section 5 are conclusions and future work.