Abstract
A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS. The chip realizes cascade folding and interpolation with resistive averaging and digital calibration. Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s. The proposed effective calibration methods could improve the static and dynamic performance of ADC.
Original language | English |
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Pages (from-to) | 393-397 |
Number of pages | 5 |
Journal | Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics |
Volume | 31 |
Issue number | 4 |
Publication status | Published - Aug 2011 |
Externally published | Yes |
Keywords
- Analog-to-digital conversion
- Folding and interpolation
- Offset calibration
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Zhang, Y., Li, X., Zhang, M., Liu, A., Qian, F., & Chen, C. (2011). A single channel 8 bit 1.4 GS/s folding and interpolation ADC. Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics, 31(4), 393-397.