A single channel 8 bit 1.4 GS/s folding and interpolation ADC

Youtao Zhang; Xiaopeng Li; Min Zhang; Ao Liu; Feng Qian; Chen Chen

A single channel 8 bit 1.4 GS/s folding and interpolation ADC

Youtao Zhang^*, Xiaopeng Li, Min Zhang, Ao Liu, Feng Qian, Chen Chen

^*Corresponding author for this work

Nanjing Electronic Devices Institute

Research output: Contribution to journal › Article › peer-review

Abstract

A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS. The chip realizes cascade folding and interpolation with resistive averaging and digital calibration. Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s. The proposed effective calibration methods could improve the static and dynamic performance of ADC.

Original language	English
Pages (from-to)	393-397
Number of pages	5
Journal	Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics
Volume	31
Issue number	4
Publication status	Published - Aug 2011
Externally published	Yes

Keywords

Analog-to-digital conversion
Folding and interpolation
Offset calibration

Cite this

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title = "A single channel 8 bit 1.4 GS/s folding and interpolation ADC",

abstract = "A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS. The chip realizes cascade folding and interpolation with resistive averaging and digital calibration. Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s. The proposed effective calibration methods could improve the static and dynamic performance of ADC.",

keywords = "Analog-to-digital conversion, Folding and interpolation, Offset calibration",

author = "Youtao Zhang and Xiaopeng Li and Min Zhang and Ao Liu and Feng Qian and Chen Chen",

year = "2011",

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language = "English",

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T1 - A single channel 8 bit 1.4 GS/s folding and interpolation ADC

AU - Zhang, Youtao

AU - Li, Xiaopeng

AU - Zhang, Min

AU - Liu, Ao

AU - Qian, Feng

AU - Chen, Chen

PY - 2011/8

Y1 - 2011/8

N2 - A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS. The chip realizes cascade folding and interpolation with resistive averaging and digital calibration. Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s. The proposed effective calibration methods could improve the static and dynamic performance of ADC.

AB - A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS. The chip realizes cascade folding and interpolation with resistive averaging and digital calibration. Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s. The proposed effective calibration methods could improve the static and dynamic performance of ADC.

KW - Analog-to-digital conversion

KW - Folding and interpolation

KW - Offset calibration

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M3 - Article

AN - SCOPUS:80053073416

SN - 1000-3819

VL - 31

SP - 393

EP - 397

JO - Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics

JF - Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics

IS - 4

ER -

A single channel 8 bit 1.4 GS/s folding and interpolation ADC

Abstract

Keywords

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