Abstract
This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) Δ Σ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply.
Original language | English |
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Article number | 8889451 |
Pages (from-to) | 356-368 |
Number of pages | 13 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 55 |
Issue number | 2 |
DOIs | |
Publication status | Published - Feb 2020 |
Keywords
- Analog-to-digital converter (ADC)
- data-weighted averaging (DWA)
- digital phase-locked loop (DPLL)
- digital-to-analog converter (DAC)
- switched-ring oscillator (SRO)
- time-domain signal processing
- time-to-digital converter (TDC)
- voltage-controlled oscillator (VCO)-based ΔΣ ADC
- ΔΣ ADC