A efficient design of a real-time FFT architecture based on FPGA

In this paper, for the need of FFT computation for synthetic aperture radar (SAR) imaging algorithm, Radix-2² Singlepath Delay Feedback (R2 ²SDF) algorithm with good realtime performance and less resources occupation is adopted. And a fixed-point module and a floating-point module were verified respectively with the implementation of FPGA. Thus the paper discusses the structure of the FFT algorithm. Compare the resource occupation and the speed of the fixedpoint module and the floating-point module. Analyse the performance of the algorithm. At last complete the SAR imaging process with fixed-point FFT algorithm, therefore save resources and give full play to the advantages of the FPGA. R2²SDF FFT need less resource, has high real-time performance, is suitable for VLSI implementation.