@inproceedings{22c912c872c8473b8ab1336345b3a104,
title = "A design of 12-bit full differential successive approximation ADC",
abstract = "A 12-bit full differential successive approximation anolog-to-digital convertor (SAR ADC) with low power dissipation is proposed in this paper. The comparator is a crucial part in SAR ADC, and its accuracy, speed and offset have an effect on the performance of ADC. In this paper, a multi-stage comparator is designed, which is composed of three stage amplifiers and a latch and the offset calibration technique is applied, too. The DAC consists of 64 unit capacitors. The circuit is designed under TSMC CMOS 0.18-mrf process. The simulation results show that under a 3.3V power supply, the performance of SNDR reaches nearly 71.25dB and the SFDR reaches nearly 80.97dB with the condition that the sampling frequency is 0.67MHz. The power consumption of SAR is about 4.5mW.",
keywords = "Multi-stage comparator, Offset calibration, SAR",
author = "Wei Gao and Lei Zhang and Xinghua Wang and Mu Yao and Peng Gao",
year = "2013",
doi = "10.1117/12.2008288",
language = "English",
isbn = "9780819495662",
series = "Proceedings of SPIE - The International Society for Optical Engineering",
booktitle = "International Conference on Graphic and Image Processing, ICGIP 2012",
note = "4th International Conference on Graphic and Image Processing, ICGIP 2012 ; Conference date: 06-10-2012 Through 07-10-2012",
}