1.15 GHz image rejection filter with 45 dB image rejection ratio and 8.4 mW DC power in 90 nm CMOS

An'an Li, Yingtao Ding, Zhiming Chen*, Baoyong Chi

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

A 1.15 GHz image rejection filter in 90 nm CMOS is presented. It consists of two band-pass filter stages and one band-stop filter stage, with the Q-enhancing and frequency stagger-tuning techniques to compensate the loss of low quality factor on-chip passive components and maintain enough bandwidth, respectively. The presented filter has been integrated in one K-band dual down-conversion super-heterodyne receiver and achieves 45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The DC power consumption is 8.4 mW.

Original languageEnglish
Pages (from-to)48-53
Number of pages6
JournalMicroelectronics Journal
Volume84
DOIs
Publication statusPublished - Feb 2019

Keywords

  • CMOS
  • Frequency stagger-tuning
  • Image rejection filter
  • Q-enhancing
  • Super-heterodyne

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