Time-Interpolation-Based Phase Detection Method for the Digital Phase-Locked Loop of a MEMS Voltage Sensor

Digital phase-locked loops (DPLLs) often suffer from limited phase resolution, dead-zone effects, and poor noise immunity when conventional digital phase detectors are used. This work proposes a time-interpolation-based phase error detection method and implements it as a time-interpolated phase detector (TIDPD) for DPLLs. The method combines oversampling, digital filtering, and interpolation to estimate zero-crossing instants of the input signal with high accuracy. In this way, the phase resolution and loop linearity are significantly improved without increasing the main clock frequency. A complete time-interpolated phase detector architecture is constructed and evaluated on a DPLL simulation platform that includes multiple noise sources and non-idealities. Simulation results show that the proposed method effectively suppresses phase noise and quantization errors, improves locking speed, and enhances long-term frequency stability. The method is suitable for closed-loop control systems that require both high accuracy and good dynamic performance.