The implementation method about verifying to VLIW DSP

Ding Xie; He Hu; Zhang Yanjun; Sun Yihe; Yu Yongkang

The implementation method about verifying to VLIW DSP

Ding Xie^*
, He Hu
, Zhang Yanjun
, Sun Yihe
, Yu Yongkang

^*此作品的通讯作者

University of Electronic Science and Technology of China
Tsinghua University

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

摘要

Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9%. This result shows the feasibility and effectiveness of our method.

源语言	英语
主期刊名	ASICON 2005
主期刊副标题	2005 6th International Conference on ASIC, Proceedings
页	673-676
页数	4
出版状态	已出版 - 2005
已对外发布	是
活动	ASICON 2005: 2005 6th International Conference on ASIC - Shanghai, 中国期限: 24 10月 2005 → 27 10月 2005

出版系列

姓名	ASICON 2005: 2005 6th International Conference on ASIC, Proceedings
卷	2

会议

会议	ASICON 2005: 2005 6th International Conference on ASIC
国家/地区	中国
市	Shanghai
时期	24/10/05 → 27/10/05

其它文件与链接

链接到 Scopus 的出版物

引用此

@inproceedings{1b6841a8329647edbf3327dc54bb0039,

title = "The implementation method about verifying to VLIW DSP",

abstract = "Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9\%. This result shows the feasibility and effectiveness of our method.",

author = "Ding Xie and He Hu and Zhang Yanjun and Sun Yihe and Yu Yongkang",

year = "2005",

language = "English",

isbn = "0780392108",

series = "ASICON 2005: 2005 6th International Conference on ASIC, Proceedings",

pages = "673--676",

booktitle = "ASICON 2005",

note = "ASICON 2005: 2005 6th International Conference on ASIC ; Conference date: 24-10-2005 Through 27-10-2005",

}

TY - GEN

T1 - The implementation method about verifying to VLIW DSP

AU - Xie, Ding

AU - Hu, He

AU - Yanjun, Zhang

AU - Yihe, Sun

AU - Yongkang, Yu

PY - 2005

Y1 - 2005

N2 - Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9%. This result shows the feasibility and effectiveness of our method.

AB - Microprocessor cores are a big challenge in the verification field because of their complexity and specific applications. Simulation-based test vector generator μGP can generate test set more efficiently than a random approach without need of skilled engineers. In this paper we establish our verification of a 9-stage pipelined DSP with VLIW architecture on assistance of a test program generator. By adding a few manual test vectors statement coverage can attain up to 99.9%. This result shows the feasibility and effectiveness of our method.

UR - https://www.scopus.com/pages/publications/33847275258

M3 - Conference contribution

AN - SCOPUS:33847275258

SN - 0780392108

SN - 9780780392106

T3 - ASICON 2005: 2005 6th International Conference on ASIC, Proceedings

SP - 673

EP - 676

BT - ASICON 2005

T2 - ASICON 2005: 2005 6th International Conference on ASIC

Y2 - 24 October 2005 through 27 October 2005

ER -

The implementation method about verifying to VLIW DSP

摘要

出版系列

会议

其它文件与链接

学术指纹

引用此