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Supporting differentiated services in computers via programmable architecture for resourcing-on-demand (PARD)

  • Jiuyue Ma
  • , Xiufeng Sui
  • , Ninghui Sun
  • , Yupeng Li
  • , Zihao Yu
  • , Bowen Huang
  • , Tianni Xu
  • , Zhicheng Yao
  • , Yun Chen
  • , Haibin Wang
  • , Lixin Zhang
  • , Yungang Bao
  • Chinese Academy of Sciences
  • University of Chinese Academy of Sciences
  • Huawei Technologies Co., Ltd.

科研成果: 期刊稿件 › 文章 › 同行评审

摘要

This paper presents PARD, a programmable architecture for resourcing-on-demand that provides a new programming interface to convey an application's high-level information like quality-of-service requirements to the hardware. PARD enables new functionalities like fully hardware-supported virtualization and differentiated services in computers. PARD is inspired by the observation that a computer is inherently a network in which hardware components communicate via packets (e.g., over the NoC or PCIe). We apply principles of software-defined networking to this intra-computer network and address three major challenges. First, to deal with the semantic gap between high-level applications and underlying hardware packets, PARD attaches a high-level semantic tag (e.g., a virtual machine or thread ID) to each memory-access, I/O, or interrupt packet. Second, to make hardware components more manageable, PARD implements programmable control planes that can be integrated into various shared resources (e.g., cache, DRAM, and I/O devices) and can differentially process packets according to tag-based rules. Third, to facilitate programming, PARD abstracts all control planes as a device file tree to provide a uniform programming interface via which users create and apply tag-based rules. Full-system simulation results show that by co-locating latency critical memcached applications with other workloads PARD can improve a four-core computer's CPU utilization by up to a factor of four without significantly increasing tail latency. FPGA emulation based on a preliminary RTL implementation demonstrates that the cache control plane introduces no extra latency and that the memory control plane can reduce queueing delay for high-priority memory-access requests by up to a factor of 5.6.

源语言英语
页(从-至)131-143
页数13
期刊ACM SIGPLAN Notices
卷50
期4
DOI
出版状态已出版 - 4月 2015
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