Sub-1-v bgr and por hybrid circuit with 2.25-μa current dissipation and low complexity

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-Tolerant power-ON/brown-out reset signal with a hysteretic window of 18-24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%-4.28%/V and temperature coefficients (TCs) of 22-32 ppm/°C across multiple chips has a power dissipation around 2.25\mu \text{W} from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ \surd Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4-100 ms.