SPCMap: A Power-Aware and Compilation-Efficient Mapping Framework for Heterogeneous CGRAs in Onboard SAR Imaging

Onboard real-time Synthetic Aperture Radar (SAR) imaging is essential for time-sensitive applications but faces strict power constraints on satellites. Heterogeneous Coarse-Grained Reconfigurable Arrays (CGRAs) with circuit-switched networks offer an efficient and flexible platform for SAR computing, yet existing mapping methods fail to jointly optimize power and compilation time efficiency. This paper introduces SPCMap, a SAR-aware mapping framework for heterogeneous CGRAs that tackles this joint challenge. SPCMap features four innovations: (1) a power-aware Modulo Routing Resource Graph (MRRG) modeling method for accurate power estimation; (2) an anchor diffusion method leveraging the multi-source convergence pattern of SAR data flows to prune the search space; (3) a non-greedy progressive search method to escape local optima; and (4) a parameterized active backtracking method for robustness. Evaluated on 13 real SAR Data Flow Graphs (DFGs) using a 12-nm CGRA platform, SPCMap achieves 100% mapping success. It reduces router power by up to 62.7%, with an average deviation of only 2.4% from the theoretical optimum, while keeping compilation time within 1.4× of the fastest greedy baseline. Ablation studies confirm the contribution of each component. In cross-platform comparisons, the proposed CGRA with SPCMap attains a leading normalized energy efficiency of 3.44×10⁷ pixel²/s/W, outperforming existing processors. SPCMap thus balances power, compilation time, and reliability, providing a practical compilation solution for energy-efficient onboard SAR imaging.