Sparsity-Based Hardware Acceleration Scheme of Matrix Realification

Bijective mapping enables automatic parameter pairing in the two-dimensional signal parameters via rotational invariance techniques (2D-ESPRIT) algorithm, thereby effectively reducing computational complexity. Within this process, the matrix realification step, compared to other parts, involves larger-scale and more complex computations, which impose a greater impact on the system's real-time performance. To optimize this step, this paper conducts an in-depth analysis of the computational flow based on the sparsity of matrices and a hardware acceleration system for matrix realification was designed on an FPGA platform. Experimental results demonstrate that the system integrates general and extended pipelines, achieving a computation error within 1.14 × 10^-4. When the number of total array elements and snapshots are 6 and 32, the system finishes computation within 2.62 µs, and reaches the maximum speedup of 8.17. Also, its resource usage remains stable across different number of total array elements and snapshots.