TY - GEN
T1 - Research on pipeline R22SDF FFT
AU - Li, Jian
AU - Liu, Feng
AU - Long, Teng
AU - Mao, Erke
PY - 2009
Y1 - 2009
N2 - The resource utilization of butterflies, multipliers, memory size, and control logic was analyzed according to several pipeline FFT processors. Radix-22 Single-path Delay Feedback (R22SDF) was proposed due to the limit of hardware resource and real-time in ASIC design; gave the scheme, pipeline architecture, flow of BFI and BFII; did Signal to Quantization Noise Ratio (SQNR) simulation for various bit-widths, round or cut off deal per stage, different input/output word lengths; implemented in Xilinx series FPGA V4SX55 with VHDL, did pulse compression in one radar project to verify R2 2SDF algorithm; R22SDF FFT need the least resource, has high real-time performance, is suitable for VLSI implementation.
AB - The resource utilization of butterflies, multipliers, memory size, and control logic was analyzed according to several pipeline FFT processors. Radix-22 Single-path Delay Feedback (R22SDF) was proposed due to the limit of hardware resource and real-time in ASIC design; gave the scheme, pipeline architecture, flow of BFI and BFII; did Signal to Quantization Noise Ratio (SQNR) simulation for various bit-widths, round or cut off deal per stage, different input/output word lengths; implemented in Xilinx series FPGA V4SX55 with VHDL, did pulse compression in one radar project to verify R2 2SDF algorithm; R22SDF FFT need the least resource, has high real-time performance, is suitable for VLSI implementation.
KW - Pipeline
KW - R2SDF FFT
KW - Real-Time
KW - Resource
UR - https://www.scopus.com/pages/publications/70350163368
U2 - 10.1049/cp.2009.0174
DO - 10.1049/cp.2009.0174
M3 - Conference contribution
AN - SCOPUS:70350163368
SN - 9781849190107
T3 - IET Conference Publications
BT - IET International Radar Conference 2009
T2 - IET International Radar Conference 2009
Y2 - 20 April 2009 through 22 April 2009
ER -