Performance Improvements in GAA NSFET Devices and Circuits Using a Hybrid Dual-κ Spacer Strategy at 3 nm Node and Beyond

The mainstream optimization scheme for parasitic capacitance using low-κ material for outer and inner spacers has drawbacks such as poor robust characteristics of materials and profile control of inner spacers, resulting in deterioration of driving performance of advanced gate-all-around (GAA) nanosheet field effect transistors (NSFETs). To overcome the problem of high parasitic capacitance in GAA NS devices, while reconciling the requirements for high-quality inner spacers and good driving performance, we propose a hybrid dual-κ spacer strategy, using low-κ material for outer spacers and more robust Si₃N₄ material for inner spacers. The proposed hybrid dual-κ spacer scheme not only solves the poor profile uniformity problem of inner spacers by using more Si₃N₄ at the inner spacer position but also optimizes the parasitic capacitance of the device by 14.51% (NMOS) and 11.70% (PMOS) than single SiN_x spacers, while maintaining its driving characteristics (10.00% (NMOS) and 17.01% (PMOS) better than single low-κ spacers) simultaneously. Circuit performances are thereby improved by 108.41% for 17-stage ring oscillators output frequency and 20.14% for write time in an SRAM unit. Therefore, the proposed scheme is qualified to provide an ideal solution for high-quality production of GAA devices and high-performance circuit applications.