Optimal design of DSP-based H.264 decoder

The embedded system suffers from the limitation of computing power and corresponding resources. Based on a general digital signal processor(DSP), two kinds of optimization techniques were proposed to enhance the performance of H.264 decoder. One was to transfer data of reference frame via DMA with a novel approach, which could increase the throughputs of external bus and strengthen computing power. The other was resorted to the block-based de-blocking filter, which not only minimized the times of external memory access, but also improved efficiency of DSP core. The experimental results show that the proposed solution improves the H.264 decoding speed by almost 60%. The optimized H.264 decoder can achieve the CIF @30 Hz video decoding on a Blackfin 533 processor operating at 526 MHz, which fully meets the requirement of real-time decoding.