@inproceedings{e2478ac22caf4658bd6c894d3751a99e,
title = "Multi-port memory design methodology based on block read and write",
abstract = "Multi-port memory design methodology based on block read/write is proposed in this paper. This new multi-port memory is constructed using 1-port memory banks and features parallel read/write access with low port access rejection probability. In comparison with conventional implementation of multi-port memory based on 1-port memory banks, the number of necessary 1-port memory banks is greatly reduced. Moreover, the complexity of switching network and arbitration circuits are also simplified. A tri-port memory is designed using off-the-shelf memory chips. Experiment results show that this multi-port memory design methodology is correct and the implemented multi-port memory performs well.",
keywords = "Interleaved memories, Memory architecture, Multiport memory, Probability",
author = "Weixing Ji and Feng Shi and Baojun Qiao and Hong Song",
year = "2007",
doi = "10.1109/ICCA.2007.4376358",
language = "English",
isbn = "1424408180",
series = "2007 IEEE International Conference on Control and Automation, ICCA",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "256--259",
booktitle = "2007 IEEE International Conference on Control and Automation, ICCA",
address = "United States",
note = "2007 IEEE International Conference on Control and Automation, ICCA ; Conference date: 30-05-2007 Through 01-06-2007",
}