Modeling and analysis of vertical noise coupling in TSV-based 3D mixed-signal integration

This paper reports on modeling and analysis of vertical noise coupling between adjacent chips in TSVs-based 3D mixed-signal integration. The coupling between clock channel in digital IC and channel routing wires (CRWs) in analog IC is studied in both frequency domain and time domain. According to physical architecture, a broadband equivalent circuit model of vertical noise coupling is proposed. The comparison of S parameters from full-wave electromagnetic (EM) simulation and a circuit model shows a good agreement. The coupling mechanism is discussed from transfer impedance between clock channel and CRWs. The impacts of design variables (such as geometry dimension, 3D stacking process, layout floorplan) on noise coupling are investigated. Four approaches are proposed to reduce the vertical noise coupling and compared with the baseline model. Finally, the time domain analysis shows that the rising/falling time determines peak-to-peak noise voltage and the far-end exhibits larger noise than the near-end.