Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequency synthesizer is based on a direct digital synthesizer (DDS)-driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneously. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low colored noise within the entire bandwidth. The designed output frequency range is 3.765-4.085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.