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Low-Latency and Area-Efficient Elliptic Curve Point Multiplication Architectures Over Koblitz Curves

  • Yujie Jiang
  • , Jingqi Zhang*
  • , An Wang
  • , Yue Hao
  • , Jiawei Wang
  • , Zhiming Chen
  • , Liehuang Zhu
  • *此作品的通讯作者
  • Beijing Institute of Technology
  • Peking University

科研成果: 期刊稿件文章同行评审

摘要

Point multiplication is the core operation in elliptic curve cryptography (ECC). Koblitz curves are a special class of curves that can utilize the Frobenius mapping to accelerate the implementation of point multiplication operations. For point multiplication on Koblitz curves, this article first proposes an optimized tNAF scalar conversion algorithm along with its corresponding hardware architecture. Additionally, for the computation of point multiplication, this article proposes two optimal computational architectures: 1) an area-efficient architecture and 2) a low-latency architecture, both of which achieve the highest pipeline efficiency. The area-efficient architecture adopts a compact four-stage pipeline with a single multiplier, ensuring high circuit area utilization efficiency while achieving relatively low computation latency. The low-latency architecture implements two-stage and three-stage pipeline designs, respectively in different binary fields, using two multipliers to reduce the clock cycles for point addition (PA) and further decrease the computation latency. The proposed architectures were implemented on Virtex-7 FPGA. For the 163), GF(2283) , and GF(2571) fields, the latency for the area-efficient architecture are 1.683 μs, 3.455 μs, and 7.511 μs, with slices usage of 3631, 7867, and 20612, and the point multiplication latency for the low-latency architecture are 1.347 μs, 3.279 μs and 7.071 μs, with slices usage of 6026, 14246, and 38515. A comparison with state-of-the-art designs shows that the proposed point multiplication architectures offer significant advantages in terms of performance. In the GF(2163) field, the computation latency of the area-efficient architecture and the low-latency architecture is reduced by at least 21.158% and 43.952%, respectively. And in the GF(2283) field, the reduction in latency is 38.985% and 42.459%, while in the GF(2571) field, the reduction in latency is 58.111% and 59.720%.

源语言英语
页(从-至)27144-27159
页数16
期刊IEEE Internet of Things Journal
12
14
DOI
出版状态已出版 - 2025
已对外发布

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