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Low cost polyimide liner formation with vacuum-assisted spin coating for through-silicon-vias

  • Beijing Institute of Technology

科研成果: 书/报告/会议事项章节会议稿件同行评审

摘要

Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named 'vacuum-assisted spin coating' for the fabrication of high aspect-ratio TSVs with polyimide (PI) liners at low cost to reduce its parasitic capacitance while increase its thermomechanical reliability. In this paper, the mechanism of the technique, liner thickness controllability, impacts of PI liner on TSV keep-out zone (KOZ), and its adaptability to 'via-last'3-D integration paradigm were addressed. Minimum step coverage of PI liner after the second coating procedure showed an increase from 32.9% to 47.6%, indicating more conformal PI liners were obtained. A 3-D finite element analysis was also employed to check KOZ of TSVs with PI/SiO2 liners on P-type Si with [100] and [110] device alignment. By employing PI liners, KOZ sizes were seen a reduction of 24.2% and 25.8% on [100] and [110] direction, respectively.

源语言英语
主期刊名2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
出版商Institute of Electrical and Electronics Engineers Inc.
ISBN(电子版)9781509013999
DOI
出版状态已出版 - 5 7月 2017
活动2016 IEEE International 3D Systems Integration Conference, 3DIC 2016 - San Francisco, 美国
期限: 8 11月 201611 11月 2016

出版系列

姓名2016 IEEE International 3D Systems Integration Conference, 3DIC 2016

会议

会议2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
国家/地区美国
San Francisco
时期8/11/1611/11/16

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