LOW-COMPLEXITY IMPLEMENTATION OF PARALLEL RECEIVER FOR TERAHERTZ COMMUNICATION SYSTEM

In this paper, we propose a low-complexity implementation of parallel receiver for high-speed terahertz communication systems, where a parallel timing recovery module and a parallel equalization module are considered. To reduce the hardware cost in timing recovery module, we introduce a ROM-based parallel interpolator and a modified parallel timing error detector, which reduce time delays, lookup tables (LUTs) and digital signal processor (DSP) slices by 25%, 26%, and 36%, respectively. On the other hand, a matched filter with minimum taps is inserted into the timing recovery loop, which reduces the hardware cost compared to the matched filter placed outside the timing recovery loop. To validate the performance of our improved parallel receiver, a fixed-point simulation is performed on MATLAB platform. Moreover, an 8Gbps 16QAM parallel receiver using our improved timing recovery module is implemented on the Xilinx ZCU111 evaluation board running at the frequency of 128MHz. The simulation and implementation results show that our improved parallel receiver has a superior bit error rate (BER) performance and a low implementation complexity.