IRFPA image detail enhancement and dynamic compression technique based on FPGA

The analog video of IRFPA output is usually converted to digital video by using 14 bit AD, and many image processing are based on 14 bit digital video. Most display equipments can only represent image of 8 bit gray levels, therefore, the method of compressing IRFPA origin 14 bit image to 8 bit image greatly affects the performance of display. The technique concerning detail enhancement and dynamic compression is an important research field of infrared technology. An IR images detail enhancement and dynamic compression algorithm was realized on a designed digital processing board which used Xilinx company's XC5VLX50T FPGA as a core designed device. The algorithm was totally implemented in the FPGA by using Verilog-HDL language, consuming modest FPGA resource, whith no resources outside FPGA needed. The processing delay of the algorithm was less than 200 μs. The actual observing experiments for different scenes show that the algorithm and the way of implement are effective.