TY - GEN
T1 - Integrated Execution Specification Design and Engineering Verification for ICV Simulation Testing
AU - Yu, Yanhui
AU - Li, Jinqi
AU - Zhang, Cheng
AU - Zhang, Zhiqiang
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - Aiming at the problems in the engineering implementation of intelligent connected vehicle (ICV) simulation testing, including inconsistent requirement parsing, manual-dependent use case generation, poor cross-platform adaptability, low batch regression efficiency, and low scene reproduction consistency, this paper proposes an integrated execution specification for simulation testing covering intelligent requirement parsing, parameterized use case construction, constraint screening, instruction mapping and closed-loop execution. Taking the unified test semantics as the core, this specification establishes a multi-dimensional parameterized model and realizes pre-verification of use case validity through regulatory constraints, physical constraints and safety constraints. The standardized instruction mapping engine is adopted to convert test semantics into executable instructions of simulation platforms automatically. Engineering verification results show that the specification can greatly improve the accuracy of requirement translation, the efficiency of batch execution and the precision of scene reproduction, transforming simulation testing from "manual organization"to "specification-driven". It provides a deployable, reusable and extensible engineering method for virtual verification of intelligent connected vehicles.
AB - Aiming at the problems in the engineering implementation of intelligent connected vehicle (ICV) simulation testing, including inconsistent requirement parsing, manual-dependent use case generation, poor cross-platform adaptability, low batch regression efficiency, and low scene reproduction consistency, this paper proposes an integrated execution specification for simulation testing covering intelligent requirement parsing, parameterized use case construction, constraint screening, instruction mapping and closed-loop execution. Taking the unified test semantics as the core, this specification establishes a multi-dimensional parameterized model and realizes pre-verification of use case validity through regulatory constraints, physical constraints and safety constraints. The standardized instruction mapping engine is adopted to convert test semantics into executable instructions of simulation platforms automatically. Engineering verification results show that the specification can greatly improve the accuracy of requirement translation, the efficiency of batch execution and the precision of scene reproduction, transforming simulation testing from "manual organization"to "specification-driven". It provides a deployable, reusable and extensible engineering method for virtual verification of intelligent connected vehicles.
KW - Constraint Screening
KW - Engineering Verification
KW - Instruction Mapping
KW - Integrated Execution Specification
KW - Intelligent Connected Vehicles
KW - Parameterized Use Cases
KW - Simulation Testing
UR - https://www.scopus.com/pages/publications/105044576646
U2 - 10.1109/ISCTIS70043.2026.11572701
DO - 10.1109/ISCTIS70043.2026.11572701
M3 - Conference contribution
AN - SCOPUS:105044576646
T3 - 2026 6th International Symposium on Computer Technology and Information Science, ISCTIS 2026
SP - 1723
EP - 1728
BT - 2026 6th International Symposium on Computer Technology and Information Science, ISCTIS 2026
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 6th International Symposium on Computer Technology and Information Science, ISCTIS 2026
Y2 - 15 May 2026 through 17 May 2026
ER -