@inproceedings{eb678414314445b0a1437a0382d115a4,
title = "HyperNTT: An Ultra-High Throughput Number Theoretic Transform Accelerator for FHE",
abstract = "As the most computationally intensive operator in fully homomorphic encryption (FHE), the number theoretic transform (NTT) critically determines FHE's computational efficiency. In this paper, we propose HyperNTT, an ultra-high throughput NTT accelerator. Its conflict-free dataflow eliminates transposition overhead in the four-step NTT algorithm, while ping-pong buffering enables stall-free pipelined execution. We further introduce a low-cost FPGA-optimized Montgomery modular reduction circuit to minimize DSP usage without sacrificing frequency. Experiments show that HyperNTT outperforms comparable state-of-the-art designs, delivering up to a 130.2× improvement in throughput. Its overall performance, measured in area time product (ATP), is enhanced by 2.1× to 16.8×.",
keywords = "Cryptography, FPGA, Hardware Accelerator, Number Theoretic Transform",
author = "Yan Xu and Xiyan Dong and Jiarui Wang and Leyan Zhang and An Wang and Xinghua Wang and Liehuang Zhu and Jingqi Zhang",
note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026 ; Conference date: 24-05-2026 Through 27-05-2026",
year = "2026",
doi = "10.1109/ISCAS66217.2026.11562554",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2748--2752",
booktitle = "ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems",
address = "United States",
}