TY - GEN
T1 - High-Resolution Fabrication of One-Dimensional SWCNTs Transistors Using Thermal Scanning Probe Lithography
AU - Li, Hongtao
AU - Hu, Ziying
AU - Jin, Zeming
AU - Liu, Xia
AU - Wang, Yeliang
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - One-dimensional materials, such as carbon nanotubes (CNTs), are promising building blocks for next-generation nano-electronic devices, yet their device fabrication remains challenging due to damage and alignment limitations in conventional lithography. Here, we demonstrate a single-walled carbon nanotube (SWCNT) one-dimensional transistor fabrication approach using scanning thermal probe lithography (t-SPL). By combining atomic force microscopy (AFM) localization with a bilayer resist wet lift-off process, precisely aligned source-drain electrodes are fabricated without exposing the CNT channel to high-energy irradiation. The resulting CNT transistors exhibit clear p-type behavior with on/off current ratios exceeding 105 at room temperature and maintain stable electrical performance after long-term storage. This work highlights the advantages of t-SPL as a high-resolution, low-damage fabrication technique for CNT-based nano-electronic devices and provides a scalable processing route for one-dimensional materials.
AB - One-dimensional materials, such as carbon nanotubes (CNTs), are promising building blocks for next-generation nano-electronic devices, yet their device fabrication remains challenging due to damage and alignment limitations in conventional lithography. Here, we demonstrate a single-walled carbon nanotube (SWCNT) one-dimensional transistor fabrication approach using scanning thermal probe lithography (t-SPL). By combining atomic force microscopy (AFM) localization with a bilayer resist wet lift-off process, precisely aligned source-drain electrodes are fabricated without exposing the CNT channel to high-energy irradiation. The resulting CNT transistors exhibit clear p-type behavior with on/off current ratios exceeding 105 at room temperature and maintain stable electrical performance after long-term storage. This work highlights the advantages of t-SPL as a high-resolution, low-damage fabrication technique for CNT-based nano-electronic devices and provides a scalable processing route for one-dimensional materials.
KW - SWCNT
KW - thermal scanning probe lithography
KW - transistor
UR - https://www.scopus.com/pages/publications/105047797886
U2 - 10.1109/NEMS69704.2026.11633616
DO - 10.1109/NEMS69704.2026.11633616
M3 - Conference contribution
AN - SCOPUS:105047797886
T3 - 2026 IEEE 21st International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2026
SP - 563
EP - 566
BT - 2026 IEEE 21st International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2026
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st IEEE International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2026
Y2 - 17 April 2026 through 21 April 2026
ER -