High-Performance Bi₂O₂Se Field Effect Transistor Fabrication Using Thermal Scanning Probe Lithography

The exploration of two-dimensional (2D) materials for next-generation electronics is driven by their potential to overcome the fundamental scaling limits of silicon-based transistors. However, the practical application of 2D material field-effect transistors (FETs) faces significant challenges, including scalable and damage-free high-resolution patterning, and the integration of high-quality gate dielectrics with pristine interfaces to fully exploit their exceptional electrical properties. We demonstrate a fabrication method for two-dimensional Bi₂O₂Se field effect transistors (FETs) using thermal scanning probe lithography (t-SPL). Both a PMMA assisted transfer method and a direct transfer method were adopted to transfer the Bi₂O₂Se flakes onto a silicon substrate, and Bi₂O₂Se flakes with a minimum thickness of 10 nm were successfully transferred. The devices were fabricated using a bilayer lift-off process compatible with t-SPL. By using t-SPL, charge injection effects caused by direct laser or electron-beam irradiation were avoided, resulting in enhanced electrical properties. For the devices demonstrated in this article, a maximum on/off ratio of 10⁷ and a maximum mobility of 200 cm2•V¹•s¹ were measured. These results are comparable to other state-of-the-art studies. Our work establishes t-SPL as a high-performance patterning method for sensitive 2D materials.