FPGA implementation of SAR bi-channel synthesis based on inverse filtering

In a multi-channel synthetic aperture radar (MSAR) system, non-uniform azimuth sampling is an important factor affecting imaging. If it is not processed and then imaged directly, it will inevitably lead to deterioration of imaging performance. The channel synthesis algorithm based on inverse filtering is a method to solve this problem. However, in actual applications, it is necessary to perform specific optimization processing on the algorithm to meet real-time requirements. This paper designs a new architecture for efficient implementation of channel synthesis algorithms. The design makes full use of the parallel characteristics of FPGA to improve the speed of the algorithm. By optimizing the DDR read-write control logic, the data transfer rate is improved. Finally, the Modelsim software is used to obtain the simulation results. At 150 MHz the processing speed could reach 461.6MSamples/s (64bit/sample).