FPGA Implementation of Pulse Compression in Time Domain

This paper presents a signal processing flow based on the time-domain pulse compression algorithm, consisting of three parts: theoretical introduction, MATLAB simulation, and FPGA verification. First, after simulating the echo signal, the time-domain waveform and parameters of the matched filter coefficients are saved during MATLAB simulation. Then, VIVADO uses the ROM core to read the file and the DDS core to generate the local oscillator signal required for down-conversion. Once down-conversion is done, passes the two signals through low-pass filters separately, and finally performs time-domain pulse compression and modulus calculation. In terms of this paper, replacing most of the self-programming with instantiated IP cores has the advantages of greatly simplifying the code and improving the maintainability of the flow. Moreover, implementing pulse compression with time-domain methods has advantages over frequency-domain methods, such as reducing compilation time and saving resource consumption. Results of simulation and test represent that the signal processing flow based on the time-domain pulse compression algorithm is consistent with theoretical expectations and is suitable for processing echo signals with relatively low intermediate frequency.