FPGA design of 2-D 9/7 integer discrete wavelet transform

A real-time and parallel implementation architecture that performed a 2-D 9/7 integer discrete wavelet transform for image data compression of the new CCSDS recommendation standard is proposed using the pipeline and the module design. The architecture mainly consists of one row transform module, one column transform module and row buffers module, etc. The whole architecture is optimized to make the row transform and column transform operate in parallel. The utilization of Block-RAM in FPGA can reduce the amount of external memory and the latency. The result shows that the implementation can reduce the computation, get higher throughput, achieve higher hardware utilization and speed up the transformation.