TY - JOUR
T1 - Ferroelectric-Polarization-Modulated 2D Floating-Gate Memory Enabling a 106 On/Off Ratio under ±1 V Gate-Voltage Sweep
AU - Yu, Tianze
AU - Li, Ce
AU - Zhen, Weili
AU - Yang, Dongliang
AU - Zhang, Zirui
AU - Li, Huihan
AU - Li, Yutao
AU - Bie, Ruitong
AU - Yuan, Mingyue
AU - Sun, Linfeng
N1 - Publisher Copyright:
© 2026 American Chemical Society
PY - 2026/6/17
Y1 - 2026/6/17
N2 - Floating-gate transistors based on 2D materials have attracted great interest owing to their superior memory characteristics and high reliability. However, most reported devices still suffer from high operating voltages, limited multifunctionality, etc. Here, we proposed a ferroelectric-polarization-modulated floating-gate transistor (FMFGT) based on a CIPS/MLG/hBN/MoS2 van der Waals heterostructure. The switchable and stable ferroelectric polarization of CIPS effectively reduces the tunneling barrier, exhibiting an on/off ratio (>106) when the sweep voltage is reduced to 1 V. In addition, the FMFGT exhibits robust dynamic response under an ultrafast pulse (∼20 ns) and achieves a maximum on/off ratio exceeding 109. Furthermore, the device demonstrates controllable synaptic plasticity under diverse stimuli, facilitating the integration of multiple optoelectronic logic gates. This work provides new insights into the role of ferroelectric polarization in floating-gate devices and establishes a promising solution toward low-voltage, multifunctional memories in edge computing and artificial intelligence.
AB - Floating-gate transistors based on 2D materials have attracted great interest owing to their superior memory characteristics and high reliability. However, most reported devices still suffer from high operating voltages, limited multifunctionality, etc. Here, we proposed a ferroelectric-polarization-modulated floating-gate transistor (FMFGT) based on a CIPS/MLG/hBN/MoS2 van der Waals heterostructure. The switchable and stable ferroelectric polarization of CIPS effectively reduces the tunneling barrier, exhibiting an on/off ratio (>106) when the sweep voltage is reduced to 1 V. In addition, the FMFGT exhibits robust dynamic response under an ultrafast pulse (∼20 ns) and achieves a maximum on/off ratio exceeding 109. Furthermore, the device demonstrates controllable synaptic plasticity under diverse stimuli, facilitating the integration of multiple optoelectronic logic gates. This work provides new insights into the role of ferroelectric polarization in floating-gate devices and establishes a promising solution toward low-voltage, multifunctional memories in edge computing and artificial intelligence.
KW - ferroelectric polarization
KW - floating-gate memory
KW - optoelectronic synapses
KW - van der Waals heterostructure
UR - https://www.scopus.com/pages/publications/105042109229
U2 - 10.1021/acs.nanolett.6c00900
DO - 10.1021/acs.nanolett.6c00900
M3 - Letter
AN - SCOPUS:105042109229
SN - 1530-6984
VL - 26
SP - 7554
EP - 7563
JO - Nano Letters
JF - Nano Letters
IS - 23
ER -